|Exploring Ethernet PHYs features, faillures, and timing|
Ethernet is very ubiquitous in today's world. Many of the courseware is about ARP, DHCP, and TCP/IP. But, what happens at the layers below, that provided us with 10, 100 and 1000 megabits per second ?
- What can cause such link to fail ?
- Are there any propietary extensions known that can be triggered by older or newer hardware ?
- Which bandwidth limits apply to the physical layer, relative to the theoretical bandwidth ?
- How can one push that bandwidth limit to the fullest, so that no time on the cable gets wasted ?
- Would using a VPN or IPV6 waste bandwidth by adding more headers to each ethernet frame, or does the time-slotted nature of a real link make this less relevant ?
- There are ways to not only distribute data over ethernet, but also provide accurate time-stamping of all or specific ethernet frames. This way timing can be distributing along with data. This can be beneficial for multimedia-purposes, synchronising multiple audiostreams, or aligning delays with multiple conference-calls going on in the same room (echo cancellation).
- IEEE 1588 can be used https://en.wikipedia.org/wiki/Precision_Time_Protocol
Exploring problem space
10 megabits per second, or 10-Base-T is using manchester-coding, a simple signal with an embedded clock. In the ethernet PHY, it is converted to a 2.5 MHz, 4-bit parallel signal. When using 100 megabits per second, or 100-Base-T, 4B5B encoding is used, next to MLT-3 encoding. This allows for a few ambiguities that can be turned into (propietary) extensions between ethernet PHYs. In the ethernet PHY, these ambiguities are resolved and lead to a 25 MHz, 4-bit parallel signal to the microcontroller.
Specific PHY implementation of 10/100 megabit
Some STM32 development board have have a SMSC / Microchip ethernet PHY mounted, the LAN8742 RMII 10/100 ethernet PHY. http://ww1.microchip.com/downloads/en/DeviceDoc/8742a.pdf
It nicely details all design decisions that go into making an Ethernet link work, or potentially make it fail.
- 100 mbps TX
The bitrate after of 25 MHz/4 bits (100 mbps). After the 4B/5B encoding it is actually 125 mbps. After this is additionally, scrambled, serialized, NRZI encoded, and MLT-3 modulated onto two differential lines, amplified, and routed to a pin on the chip. External to the chip, there are four transformers that remove DC components and prevent large voltages to be dissipated by a receiving chip.
- 100 mbps RX
For reception, a clock must be recovered, as each ethernet transceiver has it's own clock and will wander tens of kHz around the advertised frequency/bitrate. On the short-term, lots of clock wandering can be expected. This clock is recovered, a PLL has a VCO that is steered towards the average bitrate the is received.The wander in speed/frequency can pose a limit on the length of a packet, in this case 1588 bytes. The end result is a 50 MHz, 2-bit wide signal transmitted to the microcontroller.
- 10 mbps TX
The signal is accepted by the PHY from the microcontroller as a 2.5 MHz 4-bit wide signal.
- 10 mbps RX
The signal is generated by the PHY to the microcontroller as a 2.5 MHz 4-bit wide signal.