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Specific PHY implementation of 10/100 megabit

Some STM32 development board have have a SMSC / Microchip ethernet PHY mounted, the LAN8742 RMII 10/100 ethernet PHY.

It nicely details all design decisions that go into making an Ethernet link work, or potentially make it fail.

  • 100 mbps TX

The bitrate after of 25 MHz/4 bits or 50 MHz/2 bits (100 mbps). After the 4B/5B encoding it is actually 125 mbps. After this is additionally, scrambled, serialized, NRZI encoded, and MLT-3 modulated onto a differential line, amplified, and routed to a pair of pins on the chip. External to the chip, there are two ethernet signal transformers that remove DC components and prevent large voltages to be dissipated by a receiving chip, preventing large DC currents and DC components of a static discharge.

  • 100 mbps RX

For reception, a clock must be recovered, as each ethernet transceiver has it's own clock and will wander tens of kHz around the advertised frequency/bitrate. On the short-term, lots of clock wandering can be expected. This clock is recovered, a PLL has a VCO that is steered towards the average bitrate the is received.The wander in speed/frequency can pose a limit on the length of a packet, in this case 1588 bytes. The end result is a 50 MHz, 2-bit wide signal transmitted to the microcontroller.

  • 10 mbps TX

The signal is accepted by the PHY from the microcontroller as a 5 MHz 2-bit wide signal. Simple manchester encoding is used @ 20 MHz, no propiery extensions in the form of 4B/5B encoded words possible.

  • 10 mbps RX

The signal is generated by the PHY to the microcontroller as a 5 MHz 2-bit wide signal.